Q2: Why are multiplexers required, as shown in Figure 4.2?
Solution: We cannot wire data lines from multiple sources together. Instead, we require a logic circuit element to select between the sources.
Q3: Match the logic design terms to their corresponding definitions.
Solution:
Combinational element: The outputs depend only on the current inputs
State element: The outputs depend on current inputs and internal stored values
Edge-triggered clocking: All state changes occur on a clock edge
Control signal: Directs operation of a functional unit or selection by a multiplexer
Data signal: Contains information that is operated on by a functional unit
Q4: The register file is a state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.
Solution: True
Q6: The single-cycle datapath conceptually described in Section 4.3 must have separate instruction and data memories, because
Solution: the processor operates in one cycle and cannot use a single-ported memory for two different accesses within that cycle.
Q8: How does the datapath in Figure 4.17 determine the outcome of a beq instruction?
Solution: The ALU subtracts the operands and asserts the Zero output if the difference is zero. That, ANDed with the Branch decode signal, controls the multiplexer to select the next PC value.
Q10: The clock cycle time for the datapath described in Section 4.4 is determined by the longest chain of functional units used for any instruction. All instructions thus take that amount of time to execute. For this reason, single-cycle implementations are the main form of processor used today.
Solution: False
Solution: We cannot wire data lines from multiple sources together. Instead, we require a logic circuit element to select between the sources.
Q3: Match the logic design terms to their corresponding definitions.
Solution:
Combinational element: The outputs depend only on the current inputs
State element: The outputs depend on current inputs and internal stored values
Edge-triggered clocking: All state changes occur on a clock edge
Control signal: Directs operation of a functional unit or selection by a multiplexer
Data signal: Contains information that is operated on by a functional unit
Q4: The register file is a state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.
Solution: True
Q6: The single-cycle datapath conceptually described in Section 4.3 must have separate instruction and data memories, because
Solution: the processor operates in one cycle and cannot use a single-ported memory for two different accesses within that cycle.
Q8: How does the datapath in Figure 4.17 determine the outcome of a beq instruction?
Solution: The ALU subtracts the operands and asserts the Zero output if the difference is zero. That, ANDed with the Branch decode signal, controls the multiplexer to select the next PC value.
Q10: The clock cycle time for the datapath described in Section 4.4 is determined by the longest chain of functional units used for any instruction. All instructions thus take that amount of time to execute. For this reason, single-cycle implementations are the main form of processor used today.
Solution: False
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