Solution:
4
Question 3: Match the following descriptions to the defined terms.
Solution:
When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute.
Solution:
When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute.
structural hazard
When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction is not yet available.
data hazard
When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected.
control hazard
Question 4: For the following RISC-V code sequence:
ld x7, 0(x3)
addi x8, x7, 1
the RISC-V pipeline can use forwarding to completely eliminate stall cycles.
Solution:
False
ld x7, 0(x3)
addi x8, x7, 1
the RISC-V pipeline can use forwarding to completely eliminate stall cycles.
Solution:
False
Question 5: How many stall cycles are required the following code sequence executing in the RISC-V pipeline, assuming all required forwarding paths are included?
slli x6, x10, 3
add x6, x6, x18
ld x20, 0(x6)
addi x28, x20, -1
Solution:
1
slli x6, x10, 3
add x6, x6, x18
ld x20, 0(x6)
addi x28, x20, -1
Solution:
1
Question 6: Branch prediction reduces the effect of branch hazards by assuming a given outcome for a branch and proceeding from that assumption, rather than waiting to ascertain the actual outcome.
Solution:
True
Solution:
True
Question 7: What is the latency, in clock cycles, for the following instruction in the RISC-V pipeline, assuming no stall cycles?
andi x30, x8, 0x0ff
Solution:
5
andi x30, x8, 0x0ff
Solution:
5
Question 9: Consider execution of a sd instruction in the RISC-V pipeline, with the instruction word being fetched in cycle n, and no stalls. In which cycle is the value of the MemWrite control signal determined, and in which cycle is it used?
Solution:
Determined in cycle n + 1, used in cycle n + 3
Solution:
Determined in cycle n + 1, used in cycle n + 3
Question 10: The pipeline registers in the RISC-V pipeline contain control signal values for use in subsequent pipeline stages.
Solution:
True
Solution:
True
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