Homework on Textbook Sections 4.7 to 4.11, 5.1 to 5.3

For Questions 1 to 5: In the following code sequence, we need to stall the RISC-V pipeline to resolve the load-use data hazard:

i1: ld   x8, 0(x$5)
i2: add  x9, x8, x10
i3: addi x9, x9, -1
i4: sd   x9, 0(x5)

Consider the cycle when i1 is in the EX stage, i2 is in the ID stage, and i3 is in the IF stage.

Question 1: What is the value of ID/EX.MemRead in this cycle?

Solution:

1

Question 2: What is the value of ID/EX.RegisterRd in this cycle?

Solution:

8

Question 3: What is the value of IF/ID.RegisterRs1 in this cycle?

Solution:

8

Question 4: What is the value of IF/ID.RegisterRs2 in this cycle?

Solution:

10

Question 5: Which instruction (i1, i2, i3, or i4) will be fetch by the IF stage in the next cycle?

Solution:

i3

Question 8: For the 2-bit branch predictor shown in Figure 4.61, label the states anti-clockwise from the bottom left as 0, 1, 2 and 3, as shown below.

Assume the initial state for a branch is state 0. A given branch has the following history (T = taken, N = not taken):

N, N, T, T, T, N, N

What is the state of the predictor after this history?

Solution:

1

For Questions 11 to 15: Consider a system using 28-bit addresses, with a direct-mapped cache of 32Kbytes and a block size of 64 bytes. The cache uses a write-through/no-allocate strategy without a write buffer.

Question 11: How many bits are required for the offset field of an address?

Solution:

6

Question 12: How many bits are required for the index field of an address?

Solution:

9

Question 13:

How many bits are required for the tag field of an address?

Solution:

13

Question 14: How many bits of storage are required for the cache, in addition to those for data storage?

Solution:

7,168

Quiz on Textbook Sections 4.1 to 4.4

Q2: Why are multiplexers required, as shown in Figure 4.2? 
Solution: We cannot wire data lines from multiple sources together. Instead, we require a logic circuit element to select between the sources.

Q3: Match the logic design terms to their corresponding definitions. 
Solution:
Combinational element: The outputs depend only on the current inputs
State element: The outputs depend on current inputs and internal stored values
Edge-triggered clocking: All state changes occur on a clock edge
Control signal: Directs operation of a functional unit or selection by a multiplexer
Data signal: Contains information that is operated on by a functional unit

Q4: The register file is a state element that consists of a set of registers that can be read and written by supplying a register number to be accessed. 
Solution: True

Q6: The single-cycle datapath conceptually described in Section 4.3 must have separate instruction and data memories, because 
 Solution: the processor operates in one cycle and cannot use a single-ported memory for two different accesses within that cycle.

Q8: How does the datapath in Figure 4.17 determine the outcome of a beq instruction? 
Solution: The ALU subtracts the operands and asserts the Zero output if the difference is zero. That, ANDed with the Branch decode signal, controls the multiplexer to select the next PC value.

Q10: The clock cycle time for the datapath described in Section 4.4 is determined by the longest chain of functional units used for any instruction. All instructions thus take that amount of time to execute. For this reason, single-cycle implementations are the main form of processor used today. 
Solution: False