Q1: For what combinations of operands can signed addition overflow?
Solution: Both operands positive or both operands negative
Q2: What usually happens when an overflow occurs during addition to calculate an address in a program?
Solution: Nothing - the overflow is ignored.
Q3: How many clock cycles would the sequential multiplier shown in Figure 3.5 of the textbook take to multiply 64-bit operands?
Solution: 64
Q4: A parallel multiplier using tree-structured stack of adders is much faster than a sequential multiplier, but at the cost of significantly more hardware resources.
Solution: True
Q5: Can we construct a fast parallel divider is a similar way to the way we make a fast parallel multiplier?
Solution: No, because we need to use the sign of the difference calculated at each step in order to perform the next step.
Q6: How many bits are used for single precision floating-point values?
Solution: 32 bits: 1 sign bit, 8 exponent bits, and 23 fraction bits
Q7: The revised IEEE 754-2008 standard added a 16-bit floating-point format with five exponent bits. What do you think is the likely range of numbers it could represent?
Solution: ±1.0000 0000 00×2^−14 to ±1.1111 1111 11×2^15, ±0, ±∞, NaN
Q8: The hardware for floating-point operations is significantly more complex than that for integer operations.
Solution: True
Q9: From the statements below, select those that correctly describe floating point instructions in the RISC-V instruction set.
Solution: Floating-point arithmetic instructions operate on different registers to integer instructions
Q10: The Intel SE2 instruction extensions provide subword parallelism by what means?
Solution: By having 128-bit wide registers and a floating-point operations on short vectors of 4 single-precision or 2 double-precision elements.
Solution: Both operands positive or both operands negative
Q2: What usually happens when an overflow occurs during addition to calculate an address in a program?
Solution: Nothing - the overflow is ignored.
Q3: How many clock cycles would the sequential multiplier shown in Figure 3.5 of the textbook take to multiply 64-bit operands?
Solution: 64
Q4: A parallel multiplier using tree-structured stack of adders is much faster than a sequential multiplier, but at the cost of significantly more hardware resources.
Solution: True
Q5: Can we construct a fast parallel divider is a similar way to the way we make a fast parallel multiplier?
Solution: No, because we need to use the sign of the difference calculated at each step in order to perform the next step.
Q6: How many bits are used for single precision floating-point values?
Solution: 32 bits: 1 sign bit, 8 exponent bits, and 23 fraction bits
Q7: The revised IEEE 754-2008 standard added a 16-bit floating-point format with five exponent bits. What do you think is the likely range of numbers it could represent?
Solution: ±1.0000 0000 00×2^−14 to ±1.1111 1111 11×2^15, ±0, ±∞, NaN
Q8: The hardware for floating-point operations is significantly more complex than that for integer operations.
Solution: True
Q9: From the statements below, select those that correctly describe floating point instructions in the RISC-V instruction set.
Solution: Floating-point arithmetic instructions operate on different registers to integer instructions
Q10: The Intel SE2 instruction extensions provide subword parallelism by what means?
Solution: By having 128-bit wide registers and a floating-point operations on short vectors of 4 single-precision or 2 double-precision elements.
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