Match the following descriptions to the terms defined:
A technique that uses main memory as a “cache” for secondary storage
Solution: virtual memory
An address in main memory
Solution: physical address
An address that corresponds to a location in virtual space and is translated by address mapping to a physical address when memory is accessed
Solution: virtual memory
The process by which a virtual address is mapped to an address used to access memory
Solution: address translation
Question 2:
In paged virtual memory, a virtual address is divided into a virtual page number and an offset within the page. The virtual page number is translated into a physical page number. The physical page number is joined with the offset to form the physical address.
Solution: True
Question 3:
Where is the page table located, and how is it found?
Solution: Located in physical memory at an address given by the Page Table Register
Question 4:
If a page of virtual memory is not resident in main memory, how is the page accessed?
Solution: When translating the virtual address, the valid bit in the page table entry is found to be 0. An exception occurs, and the handler reads the page from secondary storage.
Question 5:
Why does a virtual memory system require a translation lookaside buffer (TLB)?
Why does a virtual memory system require a translation lookaside buffer (TLB)?
Solution: Without it, each virtual memory access would require two physical memory accesses, one for the page table entry and one for the translated location.
Question 6:
What is the purpose of the reference bit in a page table entry?
What is the purpose of the reference bit in a page table entry?
Solution: It is used to implement approximate LRU replacement, by being set whenever the corresponding page is accessed.
Question 7:
Some processors use hardware to deal with a TLB miss, with circuits that locate the required PTE in physical memory and read it into the TLB. Other processors raise an exception on TLB miss and require the handler to read the PTE into the TLB. RISC-V uses the second approach.
Some processors use hardware to deal with a TLB miss, with circuits that locate the required PTE in physical memory and read it into the TLB. Other processors raise an exception on TLB miss and require the handler to read the PTE into the TLB. RISC-V uses the second approach.
Solution: True
Question 8:
Cache memory and virtual memory operate in different ways, since cache relies on locality of reference, whereas virtual memory does not.
Cache memory and virtual memory operate in different ways, since cache relies on locality of reference, whereas virtual memory does not.
Solution: False
Question 9
Match the following descriptions of causes of misses with the terms defined:
Match the following descriptions of causes of misses with the terms defined:
A cache miss caused by the first access to a block that has never been in the cache.
Solution: compulsory miss
Solution: compulsory miss
A cache miss that occurs because the cache, even with full associativity, cannot contain all the blocks needed to satisfy the request.
Solution: capacity miss
Solution: capacity miss
A cache miss that occurs in a set-associative or direct-mapped cache when multiple blocks compete for the same set and that are eliminated in a fully associative cache of the same size.
Solution: conflict miss
Solution: conflict miss
Question 10
What is meant by the term "nonblocking cache"?
Solution: A cache that allows an out-of-order processor to make references to the cache while the cache is handling an earlier miss.
What is meant by the term "nonblocking cache"?
Solution: A cache that allows an out-of-order processor to make references to the cache while the cache is handling an earlier miss.
No comments:
Post a Comment