Homework on Textbook Sections 5.4, 5.10, 5.7, 5.8, 5.13

For Questions 1 and 2

Suppose we have a processor with a base CPI of 1.3, assuming all references hit in the primary cache, and a clock rate of 1GHz. Assume a main memory access time of 150ns, including all the miss handling. Suppose the miss rate per instruction at the primary cache is 4%.

Question 1
What is the actual CPI?

Solution: 7.3

Question 2
How much faster will the processor be if we add a secondary cache that has a 10 ns access time and is large enough that the global miss rate to main memory is 1%?
Solution: 2.2813

For Questions 5 to 8
The RISC-V 32-bit architecture supports virtual memory with 32-bit virtual addresses mapping to 32-bit physical addresses. The page size is 4Kbytes, and page table entries (PTEs) are 4 bytes each.
Translation is performed using a 2-level page table structure. Bits 31:22 of a virtual address index the first-level page table. If the selected first-level PTE is valid, it points to a second-level page table. Bits 21:12 of the virtual address then index that second-level page table. If the selected second-level PTE is valid, it points to the physical page.

Question 5
How many bytes are required for the first-level page table?
Solution: 4,096

Question 6
How many bytes are required for a second-level page table?
Solution: 4,096

Question 7
If the entire virtual address space were allocated, how many bytes would be required for page tables?
Solution: 4,198,400

Question 8: If the following ranges of virtual addresses are allocated:

    0x00000000 to 0x011FFFFF
    0x10000000 to 0x1FFFFFFF
    0x7FC00000 to 0x7FFFFFFF

How many bytes would be required for page tables?
Solution: 290,816